Integrated circuits (ICs), and especially microprocessors, are becoming increasingly complex. Microprocessors are requiring increasingly more power as they become more complex. Microprocessors are also requiring additional signal inputs to facilitate their increased processing capability. A semiconductor package may use a package substrate to deliver power from a power supply and signals from outside the package to a semiconductor die. A package substrate is connected with the semiconductor die to increase the distribution area of signals moving to and from the semiconductor die. Two current methods for connecting a package substrate to a semiconductor die include a wire bond molded matrix array package (WB-MMAP) and a flip chip molded matrix array package (FC-MMAP).
FIG. 1A illustrates a semiconductor die coupled to a package substrate using a wire bond molded matrix array package (WB-MMAP). The package 10 includes a semiconductor die 12, such as a microprocessor, a chipset, a memory device, an application specific integrated circuit (ASIC), etc., mounted on a package substrate 14. The semiconductor die 12 transmits signals to and receives signals from the package substrate 14 using several bond wires 16. The bond wires 16 are typically copper or aluminum and allow electrical communication between pads on the package substrate 14 and the device side of the semiconductor die 12. The package 10 is connected to an external component through interconnect devices 18, which may be Ball Grid Array (BGA) interconnects such as solder balls and metal filled polymers, Pin Grid Array (PGA) interconnects such as pins, Land Grid Array (LGA) interconnects such as lands, etc. The die 12 and bond wires 16 are encapsulated in a molding material 20, such as an epoxy, to prevent damage.
FIG. 1B illustrates a flip chip molded matrix array package (FC-MMAP). The package substrate 30 includes a semiconductor die 32 and a package substrate 34. The semiconductor die 32 is connected with the package substrate 34 through solder bumps 36, which may be controlled collapse chip connection (C4) or other conductive bumps. The solder bumps 36 are formed on pads on the active or device side of the semiconductor die 32 before the semiconductor die 32 is mounted on the package substrate 34. The C4 bumps 36 are conductive so that the device side of the semiconductor die 32 can communicate with the package substrate 34. The signals that are traveling to and from the semiconductor die 32 are routed through the package substrate 34 and out of the package using the interconnects 38. The interconnect devices 38 may be solder balls or metal filled polymers, such as BGA interconnects, PGA interconnects, etc. The die 32 is encapsulated in a molding material 40, such as an epoxy, to prevent damage.
FIG. 1C illustrates a typical package substrate. The package substrate 50 provides a larger area to distribute signals from a die, as well as providing physical protection for the die. The package substrate 50 includes several vias 52 and planes 54. The vias 52 facilitate vertical signal travel within the substrate 50, and the planes 54 allow horizontal travel within the substrate 50. The vias 52 can connect with the bond wires 16 or the solder bumps 36. The bottom of the vias 52 can connect to the interconnects 18 or 38. FIG. 1D illustrates a bottom view of the package substrate 50. As can be seen in FIG. 1D, the bottom of the vias 52 are spread throughout the surface of the package substrate 50. A typical package substrate 50 may include several thousand vias 52. A top view of the package substrate 50 would be similar, except that the pads would conform to the connection method (wirebond or flip chip) and the size of the die.
Newer ICs that require more power and more signal interconnects may have exhausted the capacity of a single package substrate such as the package substrates 14, 34, and 50 above. As a result, when using a single package substrate for power and signal distribution, the single package substrate may limit the speed of the processor. Further, the increased resistance caused by the relatively small amount of conductive surface available in a signal package substrate may also contribute to higher operating temperatures.